As feature sizes of CMOS devices decrease to 45 nm and below, in order to substantially reduce gate tunneling current and gate resistance, eliminate polysilicon depletion effect, improve device reliability, and mitigate Fermi energy level pinning effect, it has become a consensus of the industry to replace conventional poly-Si (polysilicon)/SiO2 gate structure with metal gate/high-K dielectric layer/SiO2 interface layer gate structure. However, there are still many problems of the metal gate/high-K gate dielectric layer/SiO2 interface layer structure waiting to be solved. For example, the problems include thermal stability problem and interface state problem, and it is difficult to obtain a small EOT and a low threshold voltage. It is desirable to obtain a good-quality high-K gate dielectric film with a small EOT. Besides a proper high K value of the high-K gate dielectric material, interfacial engineering, i.e., formation of an ultra-thin SiO2 interface layer is also very important. Otherwise it is difficult to reduce the EOT, because the K value of the SiO2 interface layer is low and thus has a great influence on device performances. However, it is difficult to form the ultra-thin SiO2 interface layer, because a natural oxide layer typically has a thickness of about 5-6 Å, and the SiO2 interface layer may continue to grow during device manufacture.